HO CHI MINH UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY FOR HIGH QUALITY TRAINING

GRADUATION PROJECT
MAJOR: COMPUTER ENGINEERING TECHNOLOGY

EVALUATION OF PERFORMANCE OF CLOCK GATING
TECHNIQUES IN DIGITAL CIRCUIT DESIGN

Advisor:

PhD. Đỗ Duy Tân

Students:

Khưu Hoàng Duy - 19119082
Trương Văn Tỷ - 19119024

HO CHI MINH CITY − July/2023

THE SOCIALIST REPUBLIC OF VIETNAM

Independence – Freedom – Happiness
***

Ho Chi Minh City, July 2023
GRADUATION PROJECT ASSIGNMENT
Student Name:

Khuu Hoang Duy

Student ID: 19119082

Student Name:

Truong Van Ty

Student ID: 19119024

Major: Computer Engineering Technology
Advisor: PhD. Do Duy Tan
Date of assignment: 22 February, 2023

Date of submission: 22 June, 2023

1. Project Title:
Evaluation of performance of clock gating techniques in digital circuit design
2. Initial materials provided by the advisor:
Documents such as books and paper related to clock gating techniques.
3. Content of the project:
Present and evaluate the performance of some popular clock gating designs
- Designed the 4-bit ripple counter and applied these clock gating techniques to
evaluate the power consumption
- Analyzed the dynamic power and static power that contributes to total power
consumption
4. Results: Show waveforms when applying clock gating methods to 4-bit ripple counter
and compare power consumption for each clock gating techniques.

ADVISOR

THE SOCIALIST REPUBLIC OF VIETNAM

Independence – Freedom – Happiness
***

Ho Chi Minh City, July 2023
ADVISOR’S EVALUATION SHEET
Student Name:

Khuu Hoang Duy

Student ID: 19119082

Student Name:

Truong Van Ty

Student ID: 19119024

Major: Computer Engineering Technology
Project Title: Evaluation of performance of clock gating techniques in digital circuit
design
Advisor: PhD. Do Duy Tan
EVALUATION
1. Content of the project:
Present and evaluate the performance of some popular clock gating designs
2. Strengths:
Evaluate multiple clock gating techniques.
3. Weakness:
- Show the new contributions of the project compared with the existing ones.
- Clearly explain the simulation results showed in related figures.
- Check typos and grammar mistakes.
4. Approval for oral defense? (Approved or denied)
Approved
5. Overall evaluation:
Good
6. Mark: 8.5 (In words: eight point five)
ADVISOR

ĐẠI HỌC SƯ PHẠM KỸ THUẬT

CỘNG HOÀ XÃ HỘI CHỦ NGHĨA VIỆT
NAM

THÀNH PHỐ HỒ CHÍ MINH

Độc lập – Tự Do – Hạnh phúc

KHOA ĐÀO TẠO CHẤT LƯỢNG CAO

Tp. HCM, ngày 12 tháng
...

...
t of this topic, such
as:
❖

Further research on new Clock gating techniques. Due to the continuous
development of technology, new research may bring significant improvements
in performance.

❖

Implement real-world simulations on FPGA kits to provide a more
comprehensive evaluation of system functionality and performance.

❖

Apply real − world designs such as IoT, artificial intelligence, etc. Because these
fields also have constraints on performance requirements for efficient and power
− saving designs.

36

REFERENCES
[1]. Neil H. E. Weste and David Money Harris, “CMOS VLSI Design - A Circuit and
System Perspective”, 2011 - Fourth Edition, page - 181.
[2]. Mahendra Pratap Dev, Deepak Baghel, Bishwajeet Pandey, Manisha Pattanaik and
Anupam Shukla, “Clock Gated Low Power Sequential Circuit Design”, VLSI Design
Lab – Indian Institute of Information Technology, 2013.
[3]. Jagrit Kathuria, M. Ayoubkhan and Arti Noor, “A Review of Clock Gating
Techniques”, MIT International Journal of Electronics and Communication
Engineering Vol. 1 No. 2 Aug 2001 pp 106-114.
[4]. Saurabh Kshirsagar and Dr. M B Mali, “A Review of Clock gating Techniques in
Low Power Applications”, IJIRSET – Vol. 4, June 2015.
[5]. Michael Keating, David Flynn, Robert Altken, Alan Gibbons and Kaijian Shi, “Low
Power Methodology Manual for System-on-Chip Design”, 2008.
[6]. Tamil Chindhu S and Shanmugasundaram N, “Clock Gating Techniques: An
Overview”, Mahendra Engineering College – India, 2-3 March 2018.

37

APPENDIX

Code Gate based CG
module GateBasedClockGating(
output [3:0]q,
input en,
input clk,
input rst )
and(gCLK,en,clk)
ripplecounter rp1(q,gCLK,rst)
endmodule

Code Latch based CG
module LatchBasedClockGating(
output [3:0]q,
output gclk,
input en,
input clk,
input rst )
wire out_latch
wire gCLK
dLatch dLatch1(out_latch,en,clk,rst)
and(gCLK,out_latch,clk)
ripplecounter rp1(q,gCLK,rst)
assign gclk = gCLK
endmodule

38

Code Flip-flop based CG
module FlipflopBasedClockGating(
output [3:0]q,
input en,
input clk,
input rst )
wire out_dff
dff dff1(out_dff,en,clk,rst)
and(gCLK,out_dff,clk)
ripplecounter rp1(q,gCLK,rst)
endmodule

Code NewGated based CG
module NewGatedClockGating(
output [3:0]q,
output gclk,
input en,
input clk,
input rst )
wire cclk wire x
wire out_latch wire gCLK
dLatch dLatch1(out_latch,en,cclk,rst)
xnor(x,en,out_latch)
or(cclk,x,clk)
and(gCLK,out_latch,clk)
ripplecounter rp1(q,gCLK,rst)
assign gclk = gCLK
endmodule

39