HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY FOR INTERNATIONAL EDUCATION

GRADUATION PROJECT

INTEGRATING THE SUPERSCALAR
ARCHITECTURE INTO A 32-BIT RISC-V CPU

PHẠM QUANG MINH
Student ID: 20119181
Major: COMPUTER ENGINEERING

Ho Chi Minh City, June 2024
1

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY FOR INTERNATIONAL EDUCATION

GRADUATION PROJECT

INTEGRATING THE SUPERSCALAR
ARCHITECTURE INTO A 32-BIT RISC-V CPU

PHẠM QUANG MINH
Student ID: 20119181
Major: COMPUTER ENGINEERING
Advisor: TRƯƠNG NGỌC SƠN, Assoc. Prof.

Ho Chi Minh City, June 2024
2

3

4

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

Ho Chi Minh City, July 02, 2024

PRE-DEFENSE EVALUATION SHEET
Student name: Pham Quang Minh

Student ID: 20119181

Major: Computer Engineering Technology
Project title: Integrating the superscalar architecture into a 32-bit RISC-V CPU Name
of Reviewer: Do Duy Tan, Ph.D.

EVALUATION
1. Content and workload of the project
The content is appropriate for the topic of student’s thesis.
2. Strengths:
The thesis is well-organized and written.
3. Weaknesses:
- Clearly explain the block diagrams in Chapter 3
- Clearly explain simulation results in Chapter 4 e.g., adding some marks/highlights in the
figures.
4. Approval for oral defense? (Approved or denied)
Approved
5. Overall evaluation: (Excellent, Good, Fair, Poor)
Good
6. Mark: 8.5 (in words: Eight point five)
Ho Chi Minh City, July 02, 2024

REVIEWER
(Sign with full name)

5

THE SOCIALIST REPUBLIC OF VIETNAM

Independence – Freedom– Happiness


EVALUATION SHEET OF
DEFENSE COMMITTEE MEMBER
Student name: Phạm Quang Minh

Student ID: 2 0 1 1 9 1 8 1

Major: Computer Engineering
Project title: Integrating the Superscalar architecture into a 32-bit RISC-V CPU
Advisor: Trương Ngọc Sơn, Assoc. Prof.
Name of Defense Committee Member:
...................................................................................................................................................
EVALUATION
1. Content and workload of the project
.................................................................................................................................................
.................................................................................................................................................
.................................................................................................................
...

...
m_write,

alu_src,

reg_write, alu_op}),
.ex_pc(ex_pc),
.ex_instruction(ex_instruction),
.ex_read_data_1(ex_read_data_1),
.ex_read_data_2(ex_read_data_2),
.ex_sign_ext(ex_sign_ext),
.ex_rd(ex_rd),
.ex_control_signals(ex_control_signals)
)
// ALU Control
alu_control alu_ctrl_unit (
.opcode(ex_instruction[6:0]),
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.funct3(ex_instruction[14:12]),
.funct7(ex_instruction[31:25]),
.alu_ctrl(alu_ctrl)
)
// ALU
wire [31:0] alu_b
mux_N_bit #(.N(32)) alu_mux (
.in0(ex_read_data_2),
.in1(ex_sign_ext),
.mux_out(alu_b),
.control(alu_src)
)
alu alu_unit (
.a(ex_read_data_1),
.b(alu_b),
.alu_ctrl(alu_ctrl),
.result(ex_alu_result),
.zero(zero)
)
// EX/MEM Pipeline Register
EX_MEM ex_mem (
.clk(clk),
.rst(reset),
.ex_alu_result(ex_alu_result),
.ex_read_data_2(ex_read_data_2),
.ex_rd(ex_rd),
.ex_control_signals(ex_control_signals),
.mem_alu_result(mem_alu_result),
.mem_read_data_2(mem_read_data_2),
.mem_rd(mem_rd),
.mem_control_signals(mem_control_signals)
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)
// Data Memory
data_memory dmem (
.clk(clk),
.mem_write(mem_write),
.mem_read(mem_read),
.addr(mem_alu_result[6:0]),
.write_data(mem_read_data_2),
.read_data(mem_read_data)
)
// MEM/WB Pipeline Register
MEM_WB mem_wb (
.clk(clk),
.rst(reset),
.mem_read_data(mem_read_data),
.mem_alu_result(mem_alu_result),
.mem_rd(mem_rd),
.mem_control_signals(mem_control_signals),
.wb_read_data(wb_read_data),
.wb_alu_result(wb_alu_result),
.wb_rd(wb_rd),
.wb_control_signals(wb_control_signals)
)
// Write Back MUX
mux_N_bit #(.N(32)) wb_mux (
.in0(wb_alu_result),
.in1(wb_read_data),
.mux_out(wb_write_data),
.control(mem_control_signals[5])
)
// Next PC Calculation
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wire [31:0] pc_plus4 = pc_out + 4
wire [31:0] pc_branch = ex_pc + (ex_sign_ext 1)
mux_N_bit #(.N(32)) pc_mux (
.in0(pc_plus4),
.in1(pc_branch),
.mux_out(pc_next),
.control(branch &amp zero)
)
endmodule

Code testbench
`timescale 1ns/1ps
module tb
reg clk
reg reset
wire [31:0] instruction
wire [31:0] pc_out
parameter HALF_CYCLE = 11
parameter CYCLE = 2 * HALF_CYCLE
// Instantiate the top module
top top (
.clk(clk),
.reset(reset)
)
initial begin
clk = 0
forever #(HALF_CYCLE) clk = ~clk
end
initial begin
// Initialize signals
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reset = 1
// Apply reset
#(CYCLE)
reset = 0
#(50 * CYCLE)
$finish
end
initial begin
$monitor(Time: %0t, PC: %h, IF_Instruction1: %h, IF_Instruction2: %h, $time,
top.pc_out, top.if_instruction1, top.if_instruction2)
end
initial begin
$dumpfile(tb.vcd)
$dumpvars(0, tb)
end
endmodule

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