HO CHI MINH UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING

GRADUATION THESIS

DESIGN AND EVALUATION OF A 32X32 CROSSBAR
MEMRISTOR ARRAY USING VDD/2 AND VDD/3 SCHEMES

NGUYEN THI YEN
Student ID: 20119391
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: TRUONG NGOC SON, Assoc. Prof. PhD

Ho Chi Minh City, December 2024

HO CHI MINH UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING

GRADUATION THESIS

DESIGN AND EVALUATION OF A 32X32 CROSSBAR
MEMRISTOR ARRAY USING VDD/2 AND VDD/3 SCHEMES

NGUYEN THI YEN
Student ID: 20119391
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: TRUONG NGOC SON, Assoc. Prof. PhD

Ho Chi Minh City, December 2024

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom – Happiness
Ho Chi Minh City, December 18, 2024

GRADUATION THESIS ASSIGNMENT
Student name: Nguyen Thi Yen

Student ID: 20119391

Student name:

Student ID:

Student name:

Student ID:

Major: Computer Engineering Technology

Class: 201192B

Advisor: Truong Ngoc Son, Assoc. Prof. PhD

Phone number: (+84)

Date of assignment:

Date of submission:

1. Project title: Design and Evaluation of a 32x32 Crossbar Memristor Array Using

VDD/2 and VDD/3 Schemes.
2. Initial materials provided by the advisor:
3. Content of the project:
4. Final product:

CHAIR OF THE PROGRAM

ADVISOR

(Sign with full name)

(Sign with full name)

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom – Happiness
Ho Chi Minh City, December 18, 2024

ADVISOR’S EVALUATION SHEET
Student name: Nguyen Thi Yen

Student ID: 20119391

Student name: .............................................................

Student ID: ..................................

Student name: .............................................................

Student ID: ..................................

Major: Computer Engineering Technology
Project title: Design and Evaluation of a 32x32 Crossbar Memristor Array Using
VDD/2 and VDD/3 Schemes.
Advisor: ...................................................................................................................................
EVALUATION
1. Content of the project
...................................................................................................................................................
...................................................................................................................................................
.............
...

...
to flow even though the cell is not supposed to be active.
This leads to unwanted interference and sneak-path currents. In the VDD/3 scheme uses
lower voltage levels for the uned cell (333.3mV). These lower voltage levels reduce
the current that flows through the uned cells, effectively minimizing the sneak-path
currents.

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CHAPTER 5: CONCLUSION
5.1. Conclusion
In this thesis, the design and simulation of a 32x32 memristor crossbar array using
VDD/2 and VDD/3 biasing schemes were successfully carried out. The results
demonstrate the potential of these biasing schemes to mitigate sneak-path currents
effectively and ensure reliable operation of the ed memristors. The VDD/2 scheme
showed significant improvements in write operation accuracy by minimizing voltage
differentials across uned cells. Meanwhile, the VDD/3 scheme offered finer
control over voltage distribution, further reducing sneak-path currents and enhancing the
arrays stability. However, both schemes presented challenges in read operations due to
the influence of residual sneak-path currents. These findings validate the feasibility of
these schemes for memristor-based computing but also highlight areas requiring further
refinement.
5.2. Further Work
Future research can focus on optimizing the biasing schemes for improved readout
accuracy in large-scale memristor arrays. Specifically, refining the voltage distribution
and enhancing the sensing circuits could address the limitations observed during the
read operations. Additionally, exploring advanced materials for memristor devices and
integrating adaptive control mechanisms could significantly enhance performance.
Expanding the design to larger crossbar arrays, such as 64x64 or beyond, while
maintaining power efficiency and reliability, is another critical avenue for exploration.
Lastly, applying these optimized designs in neuromorphic computing and other highdemand fields will bridge the gap between simulation results and practical applications,
paving the way for scalable and efficient memristor based systems.

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REFERENCES
[1]

Saraju P. Mohanty, Memristor: From Basics to Deployment

[2]

Lingyun Shi, Guohao Zheng, Bobo Tian, Brahim Dkhil and Chungang Duan,

“Research progress on solutions to the sneak path issue in memristor crossbar arrays”,
10th March 2020
[3]

Dmitry Fliter, Keren Talisveyberg &amp Misbah Ramadan, Manual for Using

Memristor Models , November 2014

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APPENDICES

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