HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT
ANALYSIS OF TECHNIQUES FOR LOW POWER D FLIP-FLOP IMPLEMENTATION

NGUYEN THANH DUY THANH
Student ID: 20119157
VU DUC THOAI
Student ID: 19161029
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: DO DUY TAN, Ph.D.

Ho Chi Minh City, January 2025

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THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

Ho Chi Minh City, Dec 28, 2024
ADVISOR’S EVALUATION SHEET

Student name: Nguyen Thanh Duy Thanh

Student ID: 20119157

Student name: Vu Duc Thoai

Student ID: 19161029

Major: Computer Engineering Technology
Project title: Analysis of Techniques for Low Power D Flip-Flop Implementation.
Advisor: Do Duy Tan, Ph.D.
EVALUATION
1. Content of the project:
- The thesis meets its objectives, analyzing and enhancing low-power D FlipFlop techniques.
- A strong theoretical framework compares TSPC, MTCMOS, SVL,
Enhanced SVL, and Power Gating methods.
- Simulations highlight the modified Enhanced SVL methods effectiveness
in reducing leakage current and power.
However, some improvements are needed
• Additional experimental validation would strengthen the practicality and
reliability of the findings.
• Enhancements to the presentation are recommended for improved clarity
and coherence.
Strengths:
- Content:
• The thesis is well-structured, with logical presentation of theory,
simulations, and results.
• The team shows strong mastery of CMOS design, effectively applying
the innovative Modified Enhanced SVL method.
- Methodology:
• The study follows a systematic approach from theory to simulations and
comparative evaluations.
• Proficient use of Cadence Virtuoso demonstrates technical expertise.

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Results:
• The charts and analysis effectively demonstrate the Modified Enhanced
SVL methods superior performance in minimizing leakage current, power
dissipation, and propagation .
• The proposed method shows strong potential for applications in modern
low-power VLSI design.

Weaknesses:
- Presentation:
• The layout could be improved for better coherence and readability.
• Numerous grammatical and typographical errors throughout the thesis
require correction.
- Results:
• The project relies solely on simulations, limiting real-world
applicability.
• Environmental factors like temperature and process variations were not
considered, potentially affecting performance.
• The thesis lacks comparison with advanced technologie
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from
https://www.researchgate.net/publication/360286050.
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[13] Lakhotiya, S. A., &amp Tambat, R. V. (2014). Design of Flip-Flops for High Performance VLSI Applications Using Deep Submicron CMOS Technology. International
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