Đồ án tốt nghiệp - Research and implementation of low-power 6T sram designs using 90nm CMOS TICV

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Đồ án tốt nghiệp ngành Công nghệ Kỹ thuật máy tính - Research and implementation of low-power 6T sram designs using 90nm CMOS technology in cadence virtuoso - Trường Đại học Sư phạm Kỹ thuật Thành phố Hồ Chí Minh (HCMUTE)

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HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT
RESEARCH AND IMPLEMENTATION OF LOW-POWER 6T
SRAM DESIGNS USING 90NM CMOS TECHNOLOGY IN
CADENCE VIRTUOSO

LE TRONG HOANG
Student ID: 20119132
TRAN NGUYEN ANH KHOA
Student ID: 20119188
Major: COMPUTER ENGINEERING TECHNOLOGY

Ho Chi Minh City, June 2024

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT
RESEARCH AND IMPLEMENTATION OF LOW-POWER 6T
SRAM DESIGNS USING 90NM CMOS TECHNOLOGY IN
CADENCE VIRTUOSO

LE TRONG HOANG
Student ID: 20119132
TRAN NGUYEN ANH KHOA
Student ID: 20119188
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: TRUONG NGOC SON, Assoc. Prof.

Ho Chi Minh City, June 2024

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THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

-Ho Chi Minh City, June 24th, 2024

PRE-DEFENSE EVALUATION SHEET
Student name: Le Trong Hoang

Student ID: 20119132

Student name: Tran Nguyen Anh Khoa

Student ID: 20119188

Major: Computer Engineering Technology
Project title: Research and implementation of low-power 6T SRAM Designs using 90nm
CMOS technology in Cadence Virtuoso .
Name of Reviewer: Do Duy Tan, Ph.D.
EVALUATION
1. Content and workload of the project
The content is appropriate for the topic of student’s thesis.
2. Strengths:
.................................................................................................................................................
.................................................................................................................................................
.................................................................................................................................................
3. Weaknesses:
- Chapter 2 has a high duplication rate please revise the copied sections from source [1].
- There are references, but they do not follow the correct standards.
- Clearly explain the block diagrams in Chapter 3
- Clearly explain simulation results in Chapter 4.
4. Approval for oral defense? (Approved or denied)
Approved
5. Overall evaluation: (Excellent, Good, Fair, Poor)
Fair
6. Mark: 8.0 (in words: Eight)
Ho Chi Minh City, July 02, 2024
REVIEWER
(Sign with full name)

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THE SOCIALIST REPUBLIC OF VIETNAM

Independence – Freedom– Happiness
Ho Chi Minh City, July …, 2024

EVALUATION SHEET OF
DEFENSE COMMITTEE MEMBER
Student name: LE TRONG HOANG

Student ID:
...

...
luating another elements including area, timing, temperature
and static noise margin to find out how those elements and power after being reduced
afftect to each other.

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REFERENCES
[1] Market Monitor, “Market Analysis and Insights, Q1 2024”. [Online]. Available:
https://www.counterpointresearch.com/research_portal/market-monitor-market-analysisand-insights-q1-2024/ [Accessed Apr. 30, 2024].
[2] C. A. Teja, S. Radha, H. V. du John, and P. Nagabushanam, “Analysis of Power in
SRAM Cell with Various Pull up, Pull down and Pass Gate Transistors”, 2022 IEEE 11th
International Conference on Communication Systems and Network Technologies
(CSNT), 2022.
[3] A Pavlov, CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, United States of America: Springer Science + Business Media B.V., 2008.
[4] N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, United States of America: Edwards Brothers, 2011.
[5] Synopsys, What is Low Power Design?. [Online]. Available:
https://www.synopsys.com/glossary/what-is-low-power-design.html#c [Accessed Apr.
30, 2024].
[6] J. Panchal and V. Ramola, “DESIGN AND IMPLEMENTATION OF 6T SRAM USING FINFET WITH LOW POWER APPLICATION,” International Research Journal of
Engineering and Technology (IRJET), vol. 04, no. 07, July 2017.
[7] P. Bikki, M. K. R. T, M. Annapurna, and S. Vujwala, “Analysis of Low Power
SRAM Design with Leakage Control Techniques,” 2019 TEQIP III Sponsored International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks
(IMICPW), Tiruchirappalli, India, 2019, pp. 400-404, DOI:
10.1109/IMICPW.2019.8933178.
[8] M. M. Mustafa, “Efficient Thermal Aware Design Technique for Microprocessor,”
M.S. thesis, Salahaddin University, 2015.
[9] A. Hansraj, A. Chaudhary, and A. Rana, “Ultra Low Power SRAM Cell for High
Speed Applications using 90nm CMOS Technology,” 2020 8th International Conference
on Reliability, Infocom Technologies and Optimization (Trends and Future Directions)
(ICRITO), Noida, India, 2020, pp. 1107-1109,
DOI:10.1109/ICRITO48877.2020.9197869.
[10] X.Zhang , L.Yin, K.Ren, and J. Zhang, “Research on Simulation Design of MOS
Driver for Micro-LED”, Journal: Electronics, vol.11, pp. 2044, 2022.
[11] S. Raja, M. Kumar, and S. Gopal, Material analysis of high degree of variability in
thin CMOS for SRAM current sense amplifier, Materials Today: Proceedings, vol. 21,
2019, DOI: 10.1016/j.matpr.2019.05.444.

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