Đồ án tốt nghiệp - Design simulation and layout analysis of 6T sram circuit using TSMC 16nm TWST

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Đồ án tốt nghiệp ngành Công nghệ Kỹ thuật máy tính - Design simulation and layout analysis of 6T sram circuit using TSMC 16nm technology with synopsys tools - Trường Đại học Sư phạm Kỹ thuật Thành phố Hồ Chí Minh (HCMUTE)

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Ngày đăng	06/02/2026

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT

DESIGN SIMULATION AND LAYOUT ANALYSIS OF
6T SRAM CIRCUIT USING TSMC 16NM
TECHNOLOGY WITH SYNOPSYS TOOLS

NGUYEN THI LAM TRUC
Student ID: 20119172
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: PHAM VAN KHOA PhD.

Ho Chi Minh City, July 2024

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT

DESIGN SIMULATION AND LAYOUT ANALYSIS OF
6T SRAM CIRCUIT USING TSMC 16NM
TECHNOLOGY WITH SYNOPSYS TOOLS

NGUYEN THI LAM TRUC
Student ID: 20119172
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: PHAM VAN KHOA PhD.

Ho Chi Minh City, July 2024

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

-Ho Chi Minh City,

, 2024

GRADUATION PROJECT ASSIGNMENT
Student name: Nguyen Thi Lam Truc

Student ID: 20119172

Major: Computer Engineering Technology

Class: 20119CLA5

Advisor: Pham Van Khoa

Phone number: 0918004457

Date of assignment: _____________________ Date of submission: _____________

1. Project title: Design simulation and layout analysis of 6T SRAM circuit using TSMC 16nm
technology with Synopsys tools
2. Initial materials provided by the advisor: ___________________________________
3. Content of the project: _________________________________________________
4. Final product: ________________________________________________________
CHAIR OF THE PROGRAM

ADVISOR

(Sign with full name)

(Sign with full name)

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

-Ho Chi Minh City,

, 2024

ADVISOR’S EVALUATION SHEET
Student name: Nguyen Thi Lam Truc ........................... Student ID: 20119172..................
Major: Computer Engineering Technology............................................................................
Project title: DESIGN SIMULATION AND LAYOUT ANALYSIS OF 6T SRAM CIRCUIT
USING TSMC 16NM TECHNOLOGY WITH SYNOPSYS TOOLS ..................................
Advisor: Pham Van Khoa......................................................................................................
EVALUATION
1. Content of the project:
.................................................................................................................................................
.................................................................................................................................................

...

...
2.
[9] Custom Compiler, Synopsys, 2022. [Online]. Available:
https://www.synopsys.com/content/dam/synopsys/implementation&ampsignoff/datasheets/customcompiler-ds.pdf.
[10] Custom Waveview, Synopsys, 2013. [Online]. Available:
https://www.synopsys.com/content/dam/synopsys/verification/datasheets/Custom-WaveViewds.pdf.
[11] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel and M. Bastian, Analysis and Test of
Resistive-Open Defects in SRAM Pre-Charge Circuits, Journal of Electronic Testing: Theory
and Application, pp. 435-444, 23 3 2007.
[12] E. C. Apollos, Design Principles of SRAM Memory in Nano-CMOS Technologies, Scholar,
National Information Technology Development Agency (NITDA) Nigeria, May 2019.
[13] T. Geethumol and K. S. a. P. Dhanusha, POWER AND AREA EFFICIENT 10T SRAM WITH
IMPROVED READ STABILITY, Department of Electronics and Communication
Engineering, Saintgits College of Engineering, India, pp. 337-344, April 2017.
[14] M. Wieckowski, S. Patil and M. Margala, Portless SRAM—A High-Performance native to
the 6T Methodology, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11,,
NOVEMBER 2007.
[15] S. Rath and S. K. Panda, Analysis of 6T SRAM Cell in Different Technologies, Centurion
University of Technology &amp Management, Bhubaneswar, India, pp. 7-10, 2017.
[16] P. Athe and S. Dasgupta, A Comparative Study of 6T, 8T and 9T Decanano SRAM cell,
Electronics and Computer Engineering Dept. IIT Roorkee, pp. 889-894, October 2009.
[17] G. Tate, The Importance Of Metal Stack Compatibility For Semi IP, 4 1 2018. [Online].
Available: https://semiengineering.com/the-importance-of-metal-stack-compatibility-for-semiip/.
[18] Metal Layer Stack (metallization option) part 1, VLSI Expert, 23 October 2017. [Online].
Available: https://www.vlsi-expert.com/2017/10/metal-layer-stack-metallization-option1.html.
[19] V. Patel, Design Rule Checks (DRC) - A Practical View for 28nm Technology, einfochips ltd,
49

[Online]. Available: https://www.design-reuse.com/articles/41504/design-rule-checks-drc-apractical-view-for-28nm-technology.html.
[20] R. K. Harahap, E. Prasetyo, B. Heruseto and H. Afandi, Design Analog Layout Using
Schematic-Driven EDA Tools, Gunadarma University, Depok, Indonesia, pp. 69-72, 2015.
[21] parasitic interconnect corner (rc-corner), VLSI Expert, 26 April 2013. [Online]. Available:
https://www.vlsi-expert.com/2013/04/parasitic-interconnect-corner-rc-corner.html.

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