Đồ án tốt nghiệp - Design and performance evaluation of Risc-V processor with compressed I

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT

DESIGN AND PERFORMANCE EVALUATION OF RISC-V
PROCESSOR WITH COMPRESSED INSTRUCTIONS

NGUYEN THANH BINH
Student ID: 21161230
PHAN MINH CHIEN
Student ID: 21142450
Major: ELECTRONICS AND COMMUNICATION
ENGINEERING TECHNOLOGY
Supervisor: DO DUY TAN, PhD.

Ho Chi Minh City, July 2025

DISCLAIMER
This graduation thesis was completed as part of the requirements for the Bachelors degree
in Electronics and Telecommunications Engineering at the Ho Chi Minh City University
of Technology and Education. The content presented in this thesis is the result of my
independent research and design work, conducted under the supervision of a Ph.D. Do Duy
Tan.
Every effort has been made to ensure the accuracy, clarity, and completeness of the
information presented herein. All references to external sources of data, technical literature,
and prior research have been appropriately cited in accordance with academic integrity
standards.
The findings, interpretations, and conclusions expressed in this thesis are solely those of
the author and do not necessarily reflect the views or official policies of the Ho Chi Minh
City University of Technology and Education, its faculty, or any affiliated organizations.
This thesis is intended solely for academic and informational purposes and does not
constitute professional engineering advice.
The university and the supervising faculty bear no responsibility for any errors, omissions,
or consequences arising from the use of the information provided. Any reliance placed on
the content of this thesis is strictly at the reader’s own risk.
This research specifically addresses the implementation of a 5-stage pipelined RISC-V
processor on an FPGA platform, with integration of compressed instruction extensions
(RISC-V C-extension). It is important to note that the methods and experimental results
described were developed under specific test conditions and may not fully generalize to all
practical or industrial scenarios.
Further validation, optimization, and testing in a broader context are recommended before
applying the concepts or designs in real-world systems. Readers and future researchers are
encouraged to build upon this work with critical insight and thorough verification.
The author reserves the right to revise the content in future versions and assumes full
responsibility for the ideas and conclusions expres
...

...
pursued. The
lessons learned and methodologies applied herein will serve as a valuable stepping stone
in the authors continued journey in processor design and digital system development.

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References
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Technology Universiti Tunku Abdul Rahman Kampar, Malaysia, 2017
[6]
Ray, Achyut, “Branch prediction for a RISC-V processor core”, NTNU
Norwegian University of Science and Technology, Faculty of Information Technology and
Electrical Engineering, Department of Electronic Systems, June 2022.
[7]

Yamin Li. Computer Principles and Design in Verilog HDL, Wiley, 2015

[8]
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[9]
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[10] Stephen Smith. RISC-V Assembly Language Programming, Springer Science and
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[11] Gallmann, N., Vogel, P., Schiavone, P. D., &amp Benini, L. (2021, June). “From Swift
to Mighty: A Cost-Benefit Analysis of Ibex and CV32E40P Regarding Application
Performance, Power and Area”. Proceedings of the Workshop on Computer Architecture
Research with RISC-V, CARRV, 2021.
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