Đồ án tốt nghiệp - Design and optimization of approximate adder using advanced CMOS technology

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND
EDUCATION
FACULTY FOR HIGH QUALITY TRAINING

GRADUATION REPORT

DESIGN AND OPTIMIZATION OF APPROXIMATE
ADDER USING ADVANCED CMOS TECHNOLOGY

Student:

LUONG NGOC PHUONG QUYNH

ID:

19161050

Student:

NGUYEN PHUC HUNG

ID:

19161013

Major:

Electronics and Communications Engineering
Technology

Advisor:

PhD. PHAM VAN KHOA

Ho Chi Minh City, January 2024
I

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness
-Ho Chi Minh City, January

, 2024

GRADUATION PROJECT ASSIGNMENT
Student name: Luong Ngoc Phuong Quynh
_________________________
Student name: Nguyen Phuc Hung
__________________________

Student ID: 19161050

Advisor: Ph.D Pham Van Khoa

Phone number: 0964720967

Date of assignment: 01/09/2023

Date of submission: 12/01/2024

Student ID: 19161013

Major: Electronics and Communications Class: 1916CLA
Engineering Technology

1. Project title: Design and optimization of approximate adder using advanced CMOS
technology
2. Initial materials provided by the advisor: Materials about approximate computing,
analysis method full adders design
3. Content of the project: Discovery to high-performance adders and optimize it into
approximate adders, simulating based on 90nm cmos technology
4. Final product: Design diagrams and simulation data for XOR/XNOR circuits, Full Adder
circuits, Approximate Adder
CHAIR OF THE PROGRAM
(Sign with full name)

ADVISOR
(Sign with full name)

III

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

-Ho Chi Minh City, January , 2024

ADVISOR’S EVALUATION SHEET
Student name: LuongNgoc Phuong Quynh

Student ID: 19161050

Student name: Nguyen Phuc Hung

Student ID: 19161013

Major: Electronics and Communications Engineering Technology
Project title: Design and optimization of approximate adder using advanced CMOS
technology
Advisor: Ph.D Pham Van Khoa
EVALUATION
1. Content of the project:
Discovery to high-performance adders and optimize it into approximate adders,
simulating based on 90nm cmos technology
2. Strengths:
Learned and resreached about the most optimal full adders and designed approximate
adders such as Low-part Or Adder and Hardware Efficient Approximate Adder.
3. Weaknesses:
The performance of the 2 approximate adder (LOA and HEAA) has not been compared
resreach on other approximate adder has not been complated yet
4. Approval for oral defense? (Approved or denied)
......................................
...

...
chitecture for IOT full adder used in ultra low
power applications”. December 20,2023. Website:
https://www.researchgate.net/publication/337209197_Design_and_implementation_o
f_an_efficient_VLSI_architecture_for_IOT_full_adder_used_in_ultra_low_power_a
pplications
15. Padmanabhan Balasubramanian, Raunaq Nayar, Okkar Min and Douglas L. Maskell,
Approximator: A Software Tool for Automatic Generation of Approximate
Arithmetic Circuits. December 01,2023. Website:
https://www.mdpi.com/2073-431X/11/1/11
16. P. Balasubramanian, Douglas Maskell, Hardware Efficient Approximate Adder
Design. November 15,2023. Website: https://ieeexplore.ieee.org/document/8650127
17. Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan,Low-Power Digital
Signal Processing Using Approximate Adders. November 10, 2023. Website:
https://ieeexplore.ieee.org/document/6387646
18. K. Varnika, Approximate Adder: Lower-Part or Adder. November 18, 2023.
Website: https://www.ijitee.org/wp-content/uploads/papers/v9i7/G5832059720.pdf
19. Jin-Fa Lin, Yin-Tsung Hwang, A Novel High-Speed and Energy Efficient
10-Transistor Full Adder Design. October 18, 2023. Website:
https://ieeexplore.ieee.org/document/4195639
20. Zhixi Yang, Ajaypat Jain, Jinghang Liang, Jie Han and Fabrizio Lombardi,
Approximate XOR/XNOR-based Adders for Inexact Computing. October 12, 2023.
Website: https://ieeexplore.ieee.org/document/6720793
21. Sunghyun Kim, Youngmin Kim, Novel XNOR-based Approximate Computing for
Energy-efficient Image Processors. October 06, 2023. Website:
https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07548314

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22. Tejaswini M. L, Aishwarya H, Akhila M, B. G. Manasa, High-Speed Hybrid-Logic
Full Adder Using High-Performance 10-T XOR–XNOR Cell. October 22, 2023.
Website: https://ijarsct.co.in/Paper1845.pdf
23. Jie Han, Michael Orshansky, Approximate Computing: An Emerging Paradigm For
Energy-Efficient Design. October 31, 2023. Website:
https://ieeexplore.ieee.org/document/6569370
24. Jie Han, Michael OrshanskyQiang Xu, Todd Mytkowicz and Nam Sung Kim,
Approximate Computing: A Survey. October 2, 2023. Website:
https://ieeexplore.ieee.org/document/7348659
25. Mehedi Hasan, Uttam Kumar Saha, Afran Sorwar, Md. Ashik Zafar Dipto,
Muhammad Saddam Hossain, Hasan U. Zaman, A Novel Hybrid Full Adder Based
on Gate

Diffusion Input Technique, Transmission Gate and Static CMOS Logic.

September 15, 2023. Website: https://ieeexplore.ieee.org/document/8944888

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