Đồ án tốt nghiệp - Design and implementation of matrix multiplication on systolic array A

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT

DESIGN AND IMPLEMENTATION OF MATRIX
MULTIPLICATION ON SYSTOLIC ARRAY
ARCHITECTURE

NGUYỄN HẢI ĐĂNG
Student ID: 20119126
Major: COMPUTER ENGINEERING TECHNOLOGY
Supervisor: TRƯƠNG NGỌC SƠN, Assoc. Prof. PhD.

Ho Chi Minh City, July 2025

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

GRADUATION PROJECT

DESIGN AND IMPLEMENTATION OF MATRIX
MULTIPLICATION ON SYSTOLIC ARRAY
ARCHITECTURE

NGUYỄN HẢI ĐĂNG
Student ID: 20119126
Major: COMPUTER ENGINEERING TECHNOLOGY
Supervisor: TRƯƠNG NGỌC SƠN, Assoc. Prof. PhD.

Ho Chi Minh City, July 2025

ACKNOWLEDGEMENTS
First of all, we would like to thank Ho Chi Minh City University of Technology and
Education, where we had the chance to realize this graduation project. We have learned a
lot from this university for its good and fruitful environment. Beside the knowledge from
the lesson, we also had an opportunity to apply what we learned in practice from the real
work. Thanks to the school, we have conducted in whole process of realizing the project.
We were really fortunate to get assistance, encouragement, and motivation from a large
number of people while carrying out the project. First and foremost, we wish to thank our
lecturers, who have always inspired us with their energy and kindness. Your courses have
not only supplied us with information, but they have also motivated us to perform better.
We are immensely grateful to our lecturers, family, and friends for always being by our
side. Their kind words and support gave us the bravery and confidence to persist when
faced with difficult tasks and issues. We sincerely appreciate their attention and help.
Among all the persons we would like to thank, we would like to express our most
grateful thanks to our supervisor - Assoc. Prof. Dr. Truong Ngoc Son. Thank you very
much because you always believe in our ability even when we do not believe in ourselves.
Your clear answer, your good advice and your detailed comment help us to understand
many technical problems are complicated and give us the right direction to go.
With your help, we have learned not only the technology, but also the responsibility,
the team works and the perseverance. We will always remember your patience and your
kindness, and it will be our guide in the future academic and work. We know that our
project may still have some d
...

...
would make it
easier to integrate this technology into CNN accelerators or signal processing
devices.
• Layout-Level Implementation: Only the schematic design is implemented in this
project. Future work might include producing entire layout designs and doing
physical verification stages such as DRC (Design Rule Check) and LVS (Layout
Versus Schematic). This would prepare the design for production and bring it
closer to real-world chip implementation.

107

REFERENCES
[1] N. P. Jouppi, C. Young, N. Patil, and D. Patterson, In-datacenter performance
analysis of a tensor processing unit, Proceedings of the 44th Annual International
Symposium on Computer Architecture (ISCA), pp. 1–12, 2017.
[2] V. Sze, Y.-H. Chen, T.-J. Yang, and J. S. Emer, “Efficient processing of deep neural
networks: A tutorial and survey,” Proceedings of the IEEE, vol. 105, no. 12, pp. 2295–
2329, Dec. 2017.
[3] G. H. Golub and C. F. Van Loan, Matrix Computations, 4th ed. Baltimore, MD: Johns
Hopkins University Press, 2013, pp. 227–235.
[4] N. J. Higham, Accuracy and Stability of Numerical Algorithms, 2nd ed. Philadelphia,
PA: SIAM, 2002, pp. 150–160.
[5] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach,
6th ed. Cambridge, MA: Morgan Kaufmann, 2017, pp. 67–108.
[6] C. E. Leiserson and J. B. Saxe, “Retiming synchronous circuitry,” Algorithmica, vol.
6, no. 1, pp. 5–35, 1981.
[7] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach,
6th ed., Chapter 4: Pipelining: The Basic and Intermediate Concepts, San Francisco,
CA, USA: Morgan Kaufmann, 2017, pp. 266–334.
[8] N. J. Higham, Accuracy and Stability of Numerical Algorithms, 2nd ed. Philadelphia,
PA: SIAM, 2002, pp. 150–160.
[9] H. T. Kung, “Why systolic architectures?” Computer, vol. 15, no. 1, pp. 37–46, Jan.
1982.
[10] Y. Chen, T. Krishna, J. S. Emer, and V. Sze, Eyeriss: An energy-efficient
reconfigurable accelerator for deep convolutional neural networks, IEEE Journal of
Solid-State Circuits, vol. 52, no. 1, pp. 127-138, 2016.
[11] M. S. Hashemi, K. Rupnow, M. W. Majer, and D. Chen, “Accelerating Deep
Convolutional Neural Networks Using Specialized Hardware,” in Proceedings of the
IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig),
2016, pp. 1–8.
[12] N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuits and
Systems Perspective, 4th ed. Boston, MA: Pearson/Addison-Wesley, 2011, pp. 141 –
355.

108