Đồ án tốt nghiệp - Design and implementation of FPGA-BASED accelerator using convolutional NNFFLD

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND
EDUCATION
FACULTY OF INTERNATIONAL EDUCATION
MAJOR OF COMPUTER ENGINEERING TECHNOLOGY


GRADUATION THESIS
TOPIC:

DESIGN AND IMPLEMENTATION OF FPGA-BASED
ACCELERATOR USING CONVOLUTIONAL NEURAL
NETWORK FOR FACIAL LANDMARK DETECTION
STUDENTS:

Trần Long - 21119311

LECTURER:

Ph.D Phạm Văn Khoa

Ho Chi Minh, July 2025

DISCLAIMER
This thesis is submitted in partial fulfillment of the requirements for the degree of
Bachelor of Engineering at Ho Chi Minh City University of Technology and Education.
The work presented herein is the original work of the author, except where reference is
made to the work of others. All external sources of data, figures, and technical materials
have been duly acknowledged.
The design, implementation, and evaluation presented in this document were carried
out as part of an academic research project. The results and conclusions are based on
experiments performed under controlled laboratory conditions using the Kria KV260
Vision AI Starter Kit and the FINN framework.
This thesis does not represent the official views or positions of AMD Xilinx, PYNQ
developers, or any affiliated organizations. The hardware and software tools referenced
herein are the intellectual property of their respective owners.
The author accepts full responsibility for any errors or omissions and welcomes
constructive feedback for future improvements.

ACKNOWLEDGEMENTS
To Ho Chi Minh City University of Technology and Education, It is with the deepest
respect and heartfelt gratitude that I write these lines to honor and thank Ho Chi Minh City
University of Technology and Education the academic home that has nurtured my growth
over the past years. This university has been much more than a place of study to me. It has
been a source of inspiration, a crucible of ideas, and a vibrant community where I
discovered not only knowledge but also my own strengths and aspirations. The values
upheld by the institution academic excellence, integrity, and innovation have left a
profound imprint on my journey. I am proud to be a student molded by such a noble and
forward-looking educational environment.
My most sincere thanks go to the Faculty of International Education, where my
academic experience was not only enriched but also elevated to a global standard. The
faculty’s dynamic curriculum, international orientation, and unwavering support made
every semester a new adventure in learning. From orient
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[11] L. Petrica, T. Alonso, M. Kroes, N. Fraser, S. Cotofana, and M. Blott, “Memoryefficient dataflow inference for deep CNNs on FPGA,” arXiv preprint arXiv:2011.07317,
Nov. 2020. [Online]. Available: https://arxiv.org/abs/2011.07317
[12] V.R.S. Mani, A. Saravanaselvan, and N. Arumugam, “Performance comparison of
CNN, QNN and BNN deep neural networks for real-time object detection using ZYNQ
FPGA node,” Microelectronics Journal, vol. 119, p. 105319, Nov. 2021. doi:
10.1016/j.mejo.2021.105319
[13] M. Almghraby and A. O. Elnady, “Face Mask Detection in Real-Time using
MobileNetV2,” International Journal of Engineering and Advanced Technology (IJEAT),
vol. 10, no. 6, pp. 104–108, Aug. 2021.
Links:
[1]

Finn Document: https://xilinx.github.io/finn/

[2]
How to Use AI on the KV260 Vision Kit for Human Face Detection:
https://www.youtube.com/watch?v=L_Zd9R4ZeiI
[3]

Finn Tutorial: https://finn.readthedocs.io/en/latest/tutorials.html

[4]
Co-design CNN accelerator with FINN:
https://www.youtube.com/watch?v=zw2aG4PhzmA

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APPENDIX
AI

Artificial Intelligence

FPS

Frames Per Second

QAT

Quantization-Aware Training

CNN

Convolutional Neural Network

HLS

High-Level Synthesis

FINN

Fast Inference Neural Network

AXI

Advanced eXtensible Interface

PYNQ

Python for Zynq

MVAU

Matrix-Vector Activation Unit

DMA

Direct Memory Access

FIFO

First In, First Out

FPGA

Field-Programmable Gate Array

PS

Processing System

PL

Programmable Logic

IP

Intellectual Property

RTL

Register Transfer Level

MAC

Multiply-Accumulate

LUT

Look-Up Table

DSP

Digital Signal Processor

BRAM

Block Random Access Memory

DDR

Double Data Rate
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FF

Flip-Flop

FP

Floating-Point

INT

Integer

CPU

Central Processing Unit

GPU

Graphics Processing Unit

SoC

System on Chip

MPSoC

Multi-Processor System on Chip

OOC

Out-Of-Context (Synthesis)

MMIO

Memory-Mapped Input/Output

API

Application Programming Interface

I/O

Input/Output

SDK

Software Development Kit

ONNX

Open Neural Network Exchange

QNN

Quantized Neural Network

WFLW

Wider Facial Landmarks in the Wild

NME

Normalized Mean Error

AUC

Area Under Curve

TNS

Total Negative Slack

WNS

Worst Negative Slack

PPA

Performance, Power, Area

BRD

Board Reference Design

IPP

Image Preprocessing Pipeline
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HW

Hardware

SW

Software

API

Application Programming Interface

JTAG

Joint Test Action Group (Debug Interface)

OSD

On-Screen Display

GUI

Graphical User Interface

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