HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

CAPSTONE DESIGN PROJECT
ANALYSIS PROCESSING – IN -MEMORY ON SRAM

MAJOR OF ELECTRONICS AND TELECOMUNICATIONS

Students:
VU THANH TRUNG
ID: 19161063
Supervisor: PhD. PHAM VAN KHOA

HCMC – 07/2024
i

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY OF INTERNATIONAL EDUCATION

CAPSTONE DESIGN PROJECT

ANALYSIS PROCESSING – IN -MEMORY ON SRAM
MAJOR OF ELECTRONICS AND TELECOMUNICATIONS

Students:
VU THANH TRUNG
ID: 19161063
Supervisor: PhD. PHAM VAN KHOA

HCMC – 07/2024

ii

THE SOCIALIST REPUBLIC OF VIETNAM

Independence – Freedom– Happiness


Ho Chi Minh City, July 05, 2024

GRADUATION PROJECT ASSIGNMENT
Student name: _Vũ Thành Trung_________

Student ID: 19161063

Student name: __________________________ Student ID: ___________________
Student name: __________________________ Student ID: ___________________
Major: Electronics And Telecommunications Class: 19161CLA1
Engineering ___________________________
Supervisor: PhD. Pham Van Khoa_________ Phone number: 0857244478
Date of assignment: _____________________ Date of submission: _____________
1. Project title: __Analysis Processing – in – memory on SRAM
_______________________________________________________
2. Initial materials provided by supervisor: ___________________________________
3. Content of the project: _________________________________________________
4. Final product: ________________________________________________________
CHAIR OF THE PROGRAM

SUPERVISOR

iii

THE SOCIALIST REPUBLIC OF VIETNAM

Independence – Freedom– Happiness
-

SUPERVISOR’S EVALUATION SHEET
Student name: Vũ Thành Trung

Student ID:19161063

Student name: .................................................................

Student ID:................................

Student name: .................................................................

Student ID: ...............................

Major: Electronics And Telecommunications Engineering
Project title: Analysis Processing – in – memory on SRAM..................................................
................................................................................................................................................
Supervisor: PhD. Pham Van Khoa..........................................................................................

EVALUATION
1. Content of the project:

.............................
...

...
of Systems
Architecture 119 (2021).
[12] Jin Zhang, Zhiting Lin, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao and
Junning Chen, “An 8T SRAM Array with Configurable Word Lines for In-Memory
Computing Operation”, School of Electronics and Information Engineering, Anhui
University, Hefei 230601, China.
[13] Chuan-Jia Jhang, Cheng-Xin Xue, Je-Min Hung, Fu-Chun Chang, and Meng-Fan
Chang, “Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge
Devices”, IEEE Transactions On Circuits And Systems regular papers, vol. 68, no. 5, May
2021.
[14] S. Mittal, P. Rajput, S. Subramoney, “A survey of deep learning on CPUs:
Opportunities and co-optimizations”, IEEE Trans. Neural Netw. Learn. Syst (2021).
[15] M.-F. Chang, C.-F. Chen, T.-H. Chang, C.-C. Shuai, Y.-Y. Wang, and H. Yamauchi,
“17.3 A 28 nm 256kb 6T-SRAM with 280 mV improvement in Vmin using a dual-splitcontrol assist scheme,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,
Feb. 2015, pp. 314–315.
[16] K. Nii et al., “13.6 A 28 nm 400 MHz 4-parallel 1.6 Gsearch/s 80 Mb ternary CAM”,
IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 240–241.
[17] C.-C. Lin et al., “7.4 A 256 b-wordlength ReRAM-based TCAM with 1 ns searchtime and 14× improvement in wordlengthenergyefficiency-density product using 2.5T1R
cell,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Jan. 2016, pp.
136–137.
[18] A. Krizhevsky et al., “ImageNet classification with deep convolutional neural
networks,” in Proc. Adv. Neural Inf. Process. Syst., Dec. 2012, pp. 1097–1105.
[19] C. Szegedy et al., “Going deeper with convolutions,” in Proc. IEEE Conf. Comput.
Vis. Pattern Recognit. (CVPR), Jun. 2015, pp. 1–9.
[20] J. Zhang, Z. Wang, and N. Verma, “A machine-learning classifier implemented in a
standard 6T SRAM array,” in Proc. IEEE Symp. VLSI Circuits (VLSI-Circuits), Jun. 2016,
pp. C252–C253.
50

[21] X. Si et al., “24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit
CNN-based machine learning,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, Feb. 2019, pp. 396–398.
[22] Sarah Brooks, Anthony Cicchetti, “Design of a Low Power Latch Based SRAM Sense
Amplifier”, March 27, 2014.
[23] Sarah Brooks, Anthony Cicchetti, “Design of a Low Power Latch Based SRAM Sense
Amplifier”, March 27, 2014.
[24] A. Pavlov and Manoj Sachdev, CMOS SRAM Circuit Design and Parametric Test in
Nano-Scaled Technologies. Springer 2008.

51