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COMPUTER ORGANIZATION & ARCHITECTURE
Van-Khoa Pham (PhD.)

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Chapter 7
Input/Output

Read

Memory

Address Lines

Write
N Words
Address
Data

0

Data

System
Bus

Data Lines

N–1

Control Lines
Read

I/O Module

Write
Address

M Ports

Internal
Data

Address

Instructions

Interrupt
Signals

External
Data

I/O Module

Interrupt
Signals

External
Data

Data

Internal
Data

CPU

Control
Signals

Links to
peripheral
devices

Data

Figure 3.15 Computer Modules

Figure 7.1 Generic Model of an I/O Module

CPU-Memory-I/O Architecture
Memory

I/O
module

CPU

“CPU bus”
or
“System bus”

“Bus interface”

“I/O bus”

I/O
device

why does not connect peripherals
directly to the system bus?
 There

are a wide variety of peripherals with various methods of
operation. It would be impractical to incorporate the necessary logic
within the processor to control a range of devices.

 The data transfer rate of peripherals is often much slower than that of

the memory or processor. Thus, it is impractical to use the high-speed
system bus to communicate directly with a peripheral.
 The data transfer rate of some peripherals is faster than that of the

memory or processor. Again, the mismatch would lead to inefficiencies
if not managed properly.
 Peripherals often use different data formats and word lengths than the

computer to which they are attached.

Ethernet modem
(max speed)
Graphics display
Wi-Fi modem
(max speed)
Hard disk
Optical disc
Laser printer
Scanner
Mouse
Keyboard
101

102

103

104

105

106

107

108

Data Rate (bps)

Figure 2.1 Typical I/O Device Data Rates

109

1010

1011

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External Devices
 Provide a means of

exchanging data between the
external environment and the
computer
 Attach to the computer by a

link to an I/O module


The link is used to exchange
control, status, and data
between the I/O module and
the external device

 Peripheral device


An external device connected
to an I/O module

Three
categories:
 Human readable

Suitable for communicating with
the computer user
 Video display terminals (VDTs),
printers


 Machine readable

Suitable for communicating with
equipment
 Magnetic disk and tape systems,
sensors and actuators


 Communication


Suitable for communicating with
remote devices such as a terminal,
a machine readable device, or
another computer

Control
signals from
I/O module

Status
signals to
I/O module

Control
Logic

Data bits
to and from
I/O module

Buffer
Transducer

Data (device-unique)
to and from
environment

Figure 7.2 Block Diagram of an External Device

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Keyboard/Monitor
International Reference Alphabet
(IRA)


User provides input through the
keyboard
The monitor displays data
provided by the computer

Basi
...
--------------------------------------
... interrupt acknowledge line is daisy chained through the modules
Vector – address of the I/O module or some other unique identifier
Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine,
avoiding the need to execute a general interrupt-service routine first

Bus arbitration (vectored)
 An I/O module must first gain control of the bus before it can raise the interrupt request line
 When the processor detects the interrupt it responds on the interrupt acknowledge line
 Then the requesting module places its vector on the data lines

External device 00
External device 01

External device 07

External device 08
External device 09

External device 15

External device 56
External device 57

External device 63

Slave
82C59A
interrupt
controller
IR0
IR1 INT
IR2
IR3
IR4
IR5
IR6
IR7
Slave
82C59A
interrupt
controller
IR0
IR1 INT
IR2
IR3
IR4
IR5
IR6
IR7

Master
82C59A
interrupt
controller
IR0
IR1 INT
IR2
IR3
IR4
IR5
IR6
IR7

80386
processor
INTR

Slave
82C59A
interrupt
controller
IR0
IR1 INT
IR2
IR3
IR4
IR5
IR6
IR7

Figure 7.8 Use of the 82C59A Interrupt Controller

Power
supplies

Bi-directional
data bus
D7 - D0

+5 V
GND

Group
A
control

Data
bus
buffer
8-bit
internal
data bus

RD
WR
A1
A0
Reset
CS

Read/
write
control
logic

Group
B
control

(a) Block diagram

Group A
Port A
(8)

I/O
PA7 - PA0

Group A
Port C
upper (4)

I/O
PC7 - PC4

Group B
Port C
Lower(4)

I/O
PC3 - PC0

Group B
Port B
(8)

I/O
PB7 - PB0

PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB0
PB1
PB2

1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9 8255A 32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
(b) Pin layout

Figure 7.9 The Intel 8255A Programmable Peripheral Interface

PA4
PA5
PA6
PA7
WR
Reset
D0
D1
D2
D3
D4
D5
D6
D7
V
PB7
PB6
PB5
PB4
PB3

Interrupt
request
C3

A0
A1
A2
A3
INPUT A4
PORT A5
A6
A7

C4
C5

R0
R1
R2
R3
KEYBOARD
R4
R5
Shift
Control

Data ready
Acknowledge

82C55A
B0
B1
B2
B3
OUTPUT
B4
PORT
B5
B6
B7

Interrupt
request

C0

C1
C2
C6
C7

S0
S1
S2
S3
DISPLAY
S4
S5
Backspace
Clear

Data ready
Acknowledge
Blanking
Clear line

Figure 7.11 Keyboard/Display Interface to 82C55A

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Summary

Input/Output

Chapter 7
 External devices
 Keyboard/monitor
 Disk drive
 I/O modules
 Module function
 I/O module structure
 Programmed I/O
 Overview of programmed I/O
 I/O commands/instructions
 Direct memory access
 Drawbacks of programmed and

interrupt-driven I/O
 DMA function
 Intel 8237A DMA controller
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Interrupt-driven I/O

 Interrupt processing
 Design issues
 Intel 82C59A interrupt controller
 Intel 82C55A programmable

peripheral interface