Đồ án tốt nghiệp - Design and verification of JTAG controller

HO CHI MINH UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY FOR HIGH-QUALITY TRAINING

GRAGUATION PROJECT

DESIGN AND VERIFICATION OF
JTAG CONTROLLER

NGO NGOC THANG
Student ID: 20119159
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: Associate Professor, Ph.D. Phan Van Ca

Ho Chi Minh City, July 2025

HO CHI MINH UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY FOR HIGH-QUALITY TRAINING

GRAGUATION PROJECT

DESIGN AND VERIFICATION OF
JTAG CONTROLLER

NGO NGOC THANG
Student ID: 20119159
Major: COMPUTER ENGINEERING TECHNOLOGY
Advisor: Associate Professor, Ph.D. Phan Van Ca

Ho Chi Minh City, July 2025

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

-Ho Chi Minh City, July 07, 2025

GRADUATION PROJECT ASSIGNMENT
Student name: Ngo Ngoc Thang

Student ID: 20119159

Major: Computer Engineering Technology

Class: 2119159CLA2

Advisor: Assoc Prof, Ph.D. Phan Van Ca

Phone number:

Date of assignment:

Date of submission:

1. Project title: Design and verification of JTAG controller
2. Initial materials provided by the advisor:
3. Content of the project: The topic focuses on research and JTAG controller to implement read
and write applications into on-chip memory. JTAG controller is controlled through JTAG interface
signals. Read and write data is put into memory through APB bus and memory controller.
4. Final product: Simulate waveforms of read and write processes, run code coverage.
CHAIR OF THE PROGRAM
(Sign with full name)

ADVISOR

(Sign with full name)

Phan Văn Ca

THE SOCIALIST REPUBLIC OF VIETNAM
Independence – Freedom– Happiness

-Ho Chi Minh City, July 07, 2025

ADVISOR’S EVALUATION SHEET
Student name: Ngo Ngoc Thang

Student ID: 20119159

Major: Computer Engineering Technology
Project title: Design and verification of JTAG controller
Advisor: Assoc Prof, Ph.D. Phan Van Ca
EVALUATION
1. Content of the project:
The project focuses on designing and verifying a JTAG controller using Verilog. It enables
data read/write to on-chip memory via the APB bus. The design is based on the IEEE 1149.1
TAP controller standard and is verified through simulation and code coverage analysis using
QuestaSim.
2. Strengths:
+ Practical application of JTAG for memory programming.
+ Modular, standards-based design (IEEE 1149.1).
+ Good use of Verilog and simulation tools.
+ Comprehensive code coverage and verification.
3. Weaknesses:
+ Limited scope: focuses only on JTAG TAP controller, excludes boundary scan.
+ Not imp
...

...
WORK
5.1. CONCLUSION
The topic “Design and verification of a JTAG controller” is a simple topic designed
in Verilog language and simulated on QuestaSim software. This topic not only simulates
but also evaluates the code coverage results to help minimise errors and the
comprehensiveness of the system, helping students to be confident in the correctness of the
design. The results of the topic are similar to the set goals: the RTL design of the system,
waveform simulation results, and code coverage.
During the implementation of the project, there were challenges such as signal
synchronization between JTAG controller and APB bus encountering many difficulties and
memory access time management.
The disadvantages of the project can be mentioned as:
- Not many instructions have been integrated into the JTAG controller, so many
functions of JTAG have not been exploited.
- Using APB bus is not really optimized for this design.
- Not tested on FPGA kit.

5.2. FUTURE WORK
JTAG is a protocol with wide application in practice, so understanding this protocol
will help the development of future work, below are some suggestions for developing this
topic:
- Design and verify using UVM simulation environment.
- Use all the functions of the blocks used in the topic.
- Replace APB protocol with other AMBA protocols such as: AXI, AHP... or bridges
such as AXI-APB, AHP-APB...

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REFERENCES
[1] Test Technology Standards Committee, “IEEE STD 1149.1-2001,” IEEE-SA Standards
Board, report, Jun. 2001.
[2] “Instruction Register and instruction Decoder,” VLSI Tutorials, Jan. 27, 2023.
https://vlsitutorials.com/jtag-instruction-register-and-instruction-decoder/ (accessed Jul.
06, 2025).
[3] Corelis, Inc., “JTAG Tutorial.” [Online].

Available: https://www.corelis.com/educationdownload/JTAG-Tutorial.pdf
[4] Arm Ltd., “AMBA APB Protocol Specification,” 2003.
[5] D. R. Bolla, Keshavamurthy, and S. Palle, “DESIGN AND IMPLEMENTATION OF
ADVANCED PERIPHERAL BUS (APB) PROTOCOL IN SYSTEMVERILOG,” GIS
SCIENCE JOURNAL.
[6] A. Kumar, R. Sinha, and Department of E&ampC Engineering, NIT Jamshedpur, Jharkhand,
India, “DESIGN AND VERIFICATION ANALYSIS OF APB3 PROTOCOL WITH
COVERAGE,” journal-article, Nov. 2011.
[7] Admin, “Code coverage,” ChipVerify. https://www.chipverify.com/verification/codecoverage (accessed Jul. 02, 2025).
[8] Y.-B. Sha, M.-S. Lee, C.-N. J. Liu, and Department of Electrical Engineering, “On code
coverage measurement for Verilog-A,” IEEE, p. 115, 2004.

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